Date of Award

Fall 1-1-2025

Document Type

Dissertation

Degree Name

Doctor of Philosophy (PhD)

Department

Computer Science

First Advisor

Zhong, Lin

Abstract

A real-time decoder capable of meeting the stringent requirements for accuracy, latency, and throughput is essential for fault-tolerant quantum computing. While prior work has demonstrated progress in decoding isolated logical qubits, scaling to interacting logical qubits introduces significantly greater challenges, as all logical qubits in the system must be decoded collectively. This thesis addresses these challenges through the design and implementation of DECOARC, a vertex-level parallel decoding architecture based on the decoding graph abstraction. DECOARC organizes parallel computing resources using a hybrid tree-grid topology. We instantiate DECOARC in this work through two complementary systems: HELIOS, for single logical qubits, and DECONET, for multiple interacting logical qubits. The first implementation of DECOARC is a distributed realization of the Union-Find decoder, called HELIOS. HELIOS is the first decoder to achieve sublinear average decoding time per measurement round as code distance increases. Empirical evaluations on a Xilinx VCU129 FPGA demonstrate a decoding latency of 11.5 ns per round for distance 21, and sustained real-time decoding for distance 51 under 0.1% phenomenological noise, significantly outperforming prior decoders in speed and scalability. Building on this foundation, the second instantiation of DECOARC, DECONET, introduces a network-integrated decoding architecture that scales to thousands of logical qubits and supports logical operations implemented using lattice surgery. DECONET maintains a constant throughput and increases the latency modestly as the system scales. Specifically, it can support any arbitrary number (l) of logical qubits by increasing the compute resources by O(l × log(l)), which provides the required O(l) growth in I/O resources and increases latency by only O(log(l)). We implement an exploratory prototype, DE-CONET/HELIOS, which integrates the Helios decoder within the DecoNet architecture using five Xilinx VMK180 FPGAs. It demonstrates real-time decoding of 100 logical qubits at a distance of 5, achieving an average latency of 2.40 μs and an inverse throughput of 0.84 μs per measurement round under 0.1% phenomenological noise. Together, HELIOS and DECONET represent a significant advancement in scalable quantum error correction, bridging the gap between decoding algorithms and practical, high-throughput architectures capable of supporting fault-tolerant operations at the scale demanded by emerging quantum hardware.

Download

Share

COinS