Asynchronous RISC-V CPU Design with Pre-Silicon Validation on Synchronous FPGAs
Date of Award
Spring 2024
Document Type
Dissertation
Degree Name
Doctor of Philosophy (PhD)
Department
Electrical Engineering (ENAS)
First Advisor
Manohar, Rajit
Abstract
The design characteristics of digital asynchronous circuits differ from those of their synchronous counterparts. An average-case performance and a wide range of circuit design styles give asynchronous circuits a substantial advantage in area, power, performance, and robustness. However, developing asynchronous circuits is more difficult and time-consuming due to the lack of hardware and software support. Field-Programmable Gate Arrays (FPGAs), widely adopted in the synchronous design flow for pre-silicon circuit validation and prototyping, are not available in the asynchronous domain. Available Electronic Design Automation (EDA) tools have very limited support for asynchronous circuits. These factors limit asynchronous circuit designers' and software engineers' ability to perform proper chip and software verification. This thesis aims to close the gap in the FPGA-based pre-silicon validation of asynchronous circuits. It introduces a general approach to utilizing readily available synchronous FPGAs for asynchronous design emulation. We present an automated software framework that translates an asynchronous circuit description in ACT hardware description language (HDL) into a synthesizable, synchronous, and functionally equivalent emulation model in Verilog HDL. Our solution supports different levels of circuit abstraction and a wide range of design styles. A synchronous nature of the generated model allows it to be easily mapped onto synchronous FPGAs. This approach demonstrates a runtime speed-up of up to 10^5 x compared to the CPU-based simulation. To demonstrate the capabilities of our solution, we used our framework to design and verify an asynchronous RISC-V CPU. The CPU is fully compliant with the RISC-V specification and includes a Memory Subsystem with separate Instruction and Data caches, an Interrupt subsystem, and multiple I/O devices. We translated the design into Verilog and implemented it on the commercially available synchronous FPGA at the target clock frequency of 20 MHz. We successfully used the FPGA model to debug the CPU and device drivers and to boot Zephyr RTOS (Real-Time Operating System).
Recommended Citation
DASHKIN, RUSLAN, "Asynchronous RISC-V CPU Design with Pre-Silicon Validation on Synchronous FPGAs" (2024). Yale Graduate School of Arts and Sciences Dissertations. 1366.
https://elischolar.library.yale.edu/gsas_dissertations/1366
