Date of Award
Fall 2023
Document Type
Dissertation
Degree Name
Doctor of Philosophy (PhD)
Department
Computer Science
First Advisor
Bhattacharjee, Abhishek
Abstract
Brain-Computer Interfaces (BCIs) are our means of communicating directly with the brain. BCIs implanted on brain tissue offer the highest fidelity communication with the brain and can treat debilitating neurological disorders, control digital devices and improve our understanding of the brain. Unlocking their full potential requires devices capable of processing high data rates sensed from multiple brain regions. However, current BCIs are restricted to a single region, task/treatment, and process low data rates. This is because implantable BCIs must operate within milliwatts of power and respond in real-time within milliseconds to deliver safe treatment. These constraints run counter to the need for high processing rates or flexible, general-purpose computation to support many tasks and treatments. This dissertation demonstrates how, using aggressive cross-layer co-design, we can achieve a scalable BCI that can process state-of-the-art data rates for a wide range of complex BCI tasks, all while maintaining critical power and latency constraints necessary for safe use. This dissertation achieves this goal with two contributions. First, it explores a hardware-software co-design methodology to realize an unconventional heterogeneous reconfigurable architecture, HALO, that balances power, performance, and flexibility for BCIs. This design achieves superior performance per watt against existing BCIs and supports multiple BCI applications. Second, it develops SCALO, the first distributed brain-computer interface with multiple implants placed on different brain regions connected wirelessly. SCALO builds on top of HALO and pushes its co-design methodology to tightly integrate accelerators with storage and network. These principles allow, for the first time, a BCI that can interface with multiple brain regions using distributed processing while adhering to tight power and latency constraints. Overall, this research dramatically improves the state-of-the-art in implantable BCIs and low-power architecture design. It unlocks new treatment options for debilitating neurological disorders and new research into brain-wide network behavior. It serves as a blueprint for designing energy-efficient networked distributed systems with hardware accelerators from the ground up. The results have created a platform for physical chips and partial tapeouts for a BCI architecture. It is the first step in a long-term project to develop safe, implantable BCIs and enable state-of-art treatments for neurological disorders at the highest quality.
Recommended Citation
Sriram, Karthik, "Accelerator-Rich Computer Architectures for Brain-Computer Interfaces" (2023). Yale Graduate School of Arts and Sciences Dissertations. 1170.
https://elischolar.library.yale.edu/gsas_dissertations/1170
